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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 11c. PGA1 and PGA2 Gain Setting
Bits (PG_SET[1:0])
PG_SET1
0
0
1
PG_SET0
0
1
X
PGA GAIN
2
10
25
X = Don’t care.
Table 11d. Clock Mode and CNVST Bit (CKSEL[1:0])
CKSEL1
0
0
1
1
CKSEL0
0
1
0
1
ADC CONVERSION TYPE
Internally timed acquisitions and conversions start by writing to the ADC Conversion register
and enabling one or more channels. See the ADC Conversion Register (ADCCON) (Write
Only) section. All of the selected channels are sequentially converted each time the ADC
Conversion register is written to.
Internally timed acquisitions and conversions start by asserting a low pulse at CNVST
whenever one or more channels are enabled in the ADC Conversion register. All of the
selected channels are sequentially converted each time a low pulse is asserted at CNVST .
Reserved. Do not use.
Selected channels are converted individually each time CNVST is pulled low. Each low pulse
on CNVST converts the next channel in the sequence.
X = Don’t care.
Table 11e. ADC Reference Configuration Bits (ADCREF[1:0])
ADCREF1
0
1
1
ADCREF0
X
0
1
ADC REFERENCE
ADC uses external reference voltage supplied at the ADCREF input.
ADC uses internal reference voltage.
ADC uses internal reference voltage. Connect external decoupling capacitor at REFADC for
better noise performance.
X = Don’t care.
Table 11f. DAC Reference Configuration Bits (DACREF[1:0])
DACREF1
0
1
1
X = Don’t care.
DACREF0
X
0
1
DAC REFERENCE
DAC uses external reference voltage supplied at the DACREF input.
DAC uses internal reference voltage.
DAC uses internal reference voltage. Connect external decoupling capacitor at REFDAC for
better noise performance.
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